The following invention relates to an automatic test system for testing electronic devices and having a calibration feature for ensuring the accurate generation of test signals for a device under test.
The designing of a test system for VLSI devices presents special engineering problems. To test VLSI devices what is needed are testers with as many as 256 I/O channels, 50 MHz clock and data rates, subnanosecond timing resolution and large test pattern memories associated with each of the 256 I/O channels. Currently test systems that satisfy these criteria are extremely expensive. This is due to the fact that the best architecture for such testers requires redundant sets of tester electronics, one for each output pin of the tester. This is referred to as tester-per-pin architecture. This duplication of circuitry is desirable because with it the problems of multiplexing and cabling, that would otherwise arise with shared test circuitry, are avoided and the test circuits can be located physically adjacent each input/output pin in close proximity with the device under test. Moreover, complex test patterns may be generated since each of the input/output pin circuits are independent and have independent timing generation and output pattern acquisition.
The problem with tester-per-pin architecture is that the redundance of the pin circuits makes the test instrument very expensive. The pin electronics circuits must include precision components which ensure accuracy of all relevant electrical parameters. Duplicating these types of circuits results in a considerable increase in the overall cost of the unit.